Responsibility1.Responsible for high performance block implementation (RTL to GDSII).2.Perform block level floor planning, power grid implementation, APR placement, timing optimization, CTS and routing.3.Close the design to meet timing, power budget and area targets.4.Run physical verification flows (DRC/LVS/EM/IR), implement fixes to meet the requirements.5.Implement ECO’s to address functional bugs, timing and physical verification violations.6.Responsible for generation and maintenance of block level STA constraints and perform STA signoff checks.7.Responsible for timing model generation and support successful integration of blocks into SOC.任职资格Qualification1.5+years of hands-on experience in digital physical design.2.Master’s/Bachelor’s degree in Electrical Engineering with an emphasis in IC design3.Experience in floor planning and routing4.Good experience with Synopsys implementation tools (DC, ICC2), experience with Cadence (Innovus) implementation tool is a plus.5.Experience with Static Timing Analysis and Synopsys primeTime6.Experience in Mentor Verification tool, Calibre7.Experience in advanced process nodes (5nm) is preferred8.Proficient in TCL coding, Perl/Python knowledge is a plus9.Good written and communication skills