STA Front-end Engineer



Software Engineering
Posted on Wednesday, October 18, 2023

About the team

Based in our Singapore regional HQ office, you will be part of our IC Lab team.

What you will be responsible for:

  • Full chip and block level timing constraint development, consistent full chip and block constraint partitioning
  • Timing closure ownership throughout the entire project cycle (RTL, synthesis, and physical implementation)
  • Analysis of clock domain crossing paths at block and full chip level
  • Work with FE/IP teams to drive integration, timing, logical equivalence checking and analysis of various IPs into RTL
  • Develop/modify/run RTL logic synthesis, formal verification, power intent verification and post-synthesis timing validation flows
  • Execute low power design and physical synthesis, deploying knowledge of unified power format and power intent verification
  • Implement Functional ECOs for complex blocks
  • Some logic design in Verilog/SystemVerilog and confirmation of quality of coding through LINT and clock domain crossing flows
  • Deploy and enhance methodology and flows related to timing constraint generation and verification and timing closure
  • Work closely with chip architecture, design verification, physical design, DFT, and power teams to achieve tapeout success on designs – generally bridging the RTL and place and route
  • Work with multi-disciplinary groups to make sure RTL/Netlists are on schedule and delivered with the highest quality by incorporating automated checks at every stage of the design process

How you will stand out:

  • Bachelor’s degree in electrical engineering, computer engineering or computer science
  • 3+ years of experience working as a synthesis and/or front-end STA engineer
  • Experience in ASIC multimode constraint generation, constraint partitioning and timing closure in advanced nodes
  • Experience with test modes, mode merging to optimize physical design implementation and STA Signoff
  • Experience with power intent and upf development for block and SOC top
  • Familiar with formal verification and implementing functional ECOs
  • Knowledge of deep sub-micron FinFET technology nodes (7nm and below) timing challenges, multi-corner and multimode timing closure, process variations (AOCV, POCV based STA), voltage drop aware STA, and clock reconvergence pessimism removal
  • Hands-on experience in industry standard physical synthesis and STA tools (Synopsys DC, Primetime or equivalent)
  • Experience with clock domain crossings, DFT/Scan/MBIST/LBIST and understanding of their impact on synthesis, physical design and timing closure
  • Deep understanding of ASIC design flow, top-down and bottom-up design methodologies
  • Knowledge of low-power methodologies and leakage/dynamic power optimization flows and techniques
  • Familiar with implementation or integration of design blocks using Verilog/SystemVerilog
  • Experience with high reliability design and implementations
  • Excellent scripting skills (csh/bash, Perl, Python, TCL, Makefile etc.)
  • Self-driven individual with a can-do attitude, and an ability to work in a dynamic group environment

What you will expect:

  • Fast-growing digital assets service provider company with a supreme network of investors, pioneers and enthusiasts with ample knowledge and experience in the new industry;
  • Ability to contribute directly and make an impact to the future of digital asset industry;
  • The chance to build up new things/processes/systems from scratch;
  • Personal accountability, fast growth and learning opportunities;
  • An inspiring working environment with dynamic workspaces, flexible work time, flat structures, great team and a start-up spirit
  • Attractive salary package and welfare benefits;
  • The opportunity to grow your knowledge and career with internal and external training and mentoring resources.